• DocumentCode
    1301679
  • Title

    Conquering noise in deep-submicron digital ICs

  • Author

    Shepard, Kenneth L. ; Narayanan, Vinod

  • Author_Institution
    Dept. of Electr. Eng., Columbia Univ., New York, NY, USA
  • Volume
    15
  • Issue
    1
  • fYear
    1998
  • Firstpage
    51
  • Lastpage
    62
  • Abstract
    As feature sizes decrease and clock frequencies increase, noise is becoming a greater concern in digital IC design. The authors describe a verification metric, noise stability, which guarantees functionality in the presence of noise, and a CAD technique, static noise analysis, for applying this metric on a chipwide basis
  • Keywords
    circuit CAD; digital integrated circuits; integrated circuit noise; CAD technique; deep-submicron; digital IC design; digital ICs; functionality; noise; noise stability; static noise analysis; verification metric; 1f noise; CMOS logic circuits; CMOS technology; Circuit noise; Digital circuits; Integrated circuit noise; Logic circuits; Power supplies; Voltage; Working environment noise;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/54.655183
  • Filename
    655183
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1301679