DocumentCode
1303674
Title
SOI TFET
Enhancement via Back Biasing
Author
Guo, Anjin ; Matheu, P. ; Tsu-Jae King Liu
Author_Institution
Univ. of California, Berkeley, CA, USA
Volume
58
Issue
10
fYear
2011
Firstpage
3283
Lastpage
3285
Abstract
The effect of back biasing on the performance of a planar tunnel field-effect transistor (TFET) implemented on a silicon-on-insulator substrate is investigated. It is found that reverse back biasing reduces the subthreshold swing SS and increases the range of drain current over which SS is less than (kBT/q)ln(10); hence, it is effective for improving the TFET on/off current ratio for low operating voltages (≤ 0.5 V).
Keywords
field effect transistors; silicon-on-insulator; SOI TFET; back biasing; planar tunnel field effect transistor; silicon-on-insulator substrate; subthreshold swing; Doping; Junctions; Logic gates; Photonic band gap; Silicon; Transistors; Tunneling; Back biasing; tunnel field-effect transistor (TFET); ultra low power;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2011.2161480
Filename
5993526
Link To Document