• DocumentCode
    1303769
  • Title

    Functional Equivalence Verification Tools in High-Level Synthesis Flows

  • Author

    Mathur, Anmol ; Fujita, Masahiro ; Clarke, Edmund ; Urard, Pascal

  • Author_Institution
    Calypto Design Syst., CA, USA
  • Volume
    26
  • Issue
    4
  • fYear
    2009
  • Firstpage
    88
  • Lastpage
    95
  • Abstract
    High-level synthesis facilitates the use of formal verification methodologies that check the equivalence of the generated RTL model against the original source specification. The article provides an overview of sequential equivalence checking techniques, its challenges, and successes in real-world designs.
  • Keywords
    formal verification; high level synthesis; RTL model; formal verification methodologies; functional equivalence verification tool; high-level synthesis flows; sequential equivalence checking techniques; Algorithm design and analysis; Computer bugs; Hardware; High level synthesis; Partitioning algorithms; Software algorithms; Software performance; Software tools; State-space methods; Testing; correctness; design and test; formal analysis; functional equivalence; sequential equivalence; system-level model;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/MDT.2009.79
  • Filename
    5209966
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1303769