DocumentCode
1305900
Title
MPEG decoder architecture for embedded applications
Author
Liu, M. Norley
Author_Institution
DigiLab, TS Electron. Corp., Plano, TX, USA
Volume
42
Issue
4
fYear
1996
fDate
11/1/1996 12:00:00 AM
Firstpage
1021
Lastpage
1028
Abstract
A determinate global data transfer timing scheme will significantly reduce the complexity of global control and ease constraints on sub-modules. Such a scheme allows to construct functional modules based on an explicit performance and data flow requirement. A very low gate count hardware architecture for MPEG decoder is presented to demonstrate the concept
Keywords
decoding; logic design; logic gates; modules; telecommunication standards; video coding; MPEG decoder architecture; data flow requirement; embedded applications; functional modules; global control; global data transfer timing; performance; submodules; very low gate count hardware architecture; Consumer electronics; Costs; Decoding; Electrical equipment industry; Electronics industry; Hardware; Logic; Pipelines; Timing; Transform coding;
fLanguage
English
Journal_Title
Consumer Electronics, IEEE Transactions on
Publisher
ieee
ISSN
0098-3063
Type
jour
DOI
10.1109/30.555857
Filename
555857
Link To Document