Verification of saturation velocity lowering in MOSFET´s inversion layer

With reduction of the MOSFET´s channel length L, the drain saturation current of MOSFET´s is determined by the saturation velocity v_sat in the inversion layer. Hence, the modeling of v_sat becomes very important. In this paper, v_sat in the inversion layer has been examined by using simulation experiment. New parameter values for v_sat model in the inversion layer are proposed. In order to verify the v_sat model, the impurity profiles of MOSFET´s are calibrated to fit the threshold voltage V_th-L characteristics. Then, we validate new v_sat model by comparing the experiments of I_D-V_D characteristics of 0.35-μm CMOS with the simulations using the energy transport model (ETM)