DocumentCode
1306501
Title
Signed binary addition circuitry with inherent even parity outputs
Author
Thornton, M.A.
Author_Institution
Dept. of Comput. Syst. Eng., Arkansas Univ., Fayetteville, AR, USA
Volume
46
Issue
7
fYear
1997
fDate
7/1/1997 12:00:00 AM
Firstpage
811
Lastpage
816
Abstract
A signed binary (SE) addition circuit is presented that always produces an even parity representation of the sum word. The novelty of this design is that no extra check bits are generated or used. The redundancy inherent in a SE representation is further exploited to contain parity information
Keywords
adders; digital arithmetic; error detection; check bits; even parity representation; inherent even parity outputs; parity information; signed binary addition circuitry; Adders; Buildings; Circuits; Computer Society; Costs; Counting circuits; Delay; Digital arithmetic; Electrical fault detection; Logic circuits; Redundancy;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/12.599901
Filename
599901
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