• DocumentCode
    1307111
  • Title

    A Fast-Transient Low-Dropout Regulator With Load-Tracking Impedance Adjustment and Loop-Gain Boosting Technique

  • Author

    Or, Pui Ying ; Leung, Ka Nang

  • Author_Institution
    Dept. of Electron. Eng., Chinese Univ. of Hong Kong, Shatin, China
  • Volume
    57
  • Issue
    10
  • fYear
    2010
  • Firstpage
    757
  • Lastpage
    761
  • Abstract
    A low-voltage fast-transient low dropout (LDO) regulator compensated by an off-chip, low-equivalent-series-resistance (ESR), nanorange output capacitor is reported in this brief. The proposed load-tracking impedance adjustment and the loop-gain boosting technique make the proposed LDO regulator have fast response and small voltage spikes. The circuit is implemented by a commercial 0.35- μm CMOS technology. The chip area is 0.032 mm2. The supply voltage ranges from 1.5 to 3 V. The regulated voltage is 1.2 V to provide 0-100 mA. The quiescent current in the no-load condition is 26 μA. A 100-nF low-ESR capacitor is sufficient to stabilize the proposed LDO regulator. The measured voltage spike is 44.9 mV only, and the response time is less than 0.2 μs.
  • Keywords
    CMOS integrated circuits; capacitors; CMOS technology; fast-transient low-dropout regulator; load-tracking impedance adjustment; loop-gain boosting technique; low-equivalent-series-resistance; nanorange output capacitor; Capacitors; Impedance; Logic gates; Regulators; Time factors; Transient analysis; Transient response; Low-dropout (LDO) regulator; low-equivalent-series-resistance (ESR) capacitor;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems II: Express Briefs, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1549-7747
  • Type

    jour

  • DOI
    10.1109/TCSII.2010.2058590
  • Filename
    5559407