Gate-Field Engineering and Source/Drain Diffusion Engineering for High-Performance Si Wire GAA MOSFET and Low-Power Strategy in Sub-30-nm-Channel Regime

This paper reconsiders the design methodology of the short-channel gate-all-around (GAA) silicon-on-insulator (SOI) MOSFET and proposes an advanced concept that offers enhanced performance. The new ideas raised herein are based on gate-field engineering and source and drain (S/D) diffusion engineering. The validity of the proposal is demonstrated by device simulations. Covering the junction of a Si wire body with a relatively thick gate insulator raises the carrier density of low-doped S/D diffusion regions, resulting in a drastic reduction in the parasitic resistance (that has, up to now, hindered performance enhancement) as well as the suppression of short-channel effects due to the effective extension of channel length; it is also demonstrated that this merit can be expected even for narrow highly doped S/D diffusion regions with abrupt junctions. The simulation results suggest that 15-nm- and 20-nm-channel GAA SOI MOSFETs with the abrupt junction will be promising if the device has a body cross section of 10 nm × 10 nm and a thick insulator covers the junction. On the other hand, since it is demonstrated that the proposed GAA device must have long and graduated S/D diffusion regions in order to achieve the expected one-order-lower standby power consumption, a loss of drivability has to be accepted. However, it is shown that drivability can be improved by slightly expanding the cross section of S/D diffusion regions without seriously impacting the area penalty.