A single-chip, 1.6-billion, 16-b MAC/s multiprocessor DSP

Author

Ackland, B. ; Anesko, A. ; Brinthaupt, D. ; Daubert, S.J. ; Kalavade, A. ; Knobloch, J. ; Micca, E. ; Moturi, M. ; Nicol, C.J. ; O´Neill, J.H. ; Othmer, J. ; Säckinger, E. ; Singh, K.J. ; Sweet, J. ; Terman, C.J. ; Williams, J.

Author_Institution

Bell Labs., Lucent Technol., Holmdel, NJ, USA

Volume

35

Issue

3

fYear

2000

fDate

3/1/2000 12:00:00 AM

Firstpage

412

Lastpage

424

Abstract

An MIMD multiprocessor digital signal-processing (DSP) chip containing four 64-b processing elements (PE´s) interconnected by a 128-b pipelined split transaction bus (STBus) is presented. Each PE contains a 32-b RISC core with DSP enhancements and a 64-b single-instruction, multiple-data vector coprocessor with four 16-b MAC/s and a vector reduction unit. PEs are connected to the STBus through reconfigurable dual-ported snooping L1 cache memories that support shared memory multiprocessing using a modified-MESI data coherency protocol. High-bandwidth data transfers between system memory and on-chip caches are managed in a pipelined memory controller that supports multiple outstanding transactions. An embedded RTOS dynamically schedules multiple tasks onto the PEs. Process synchronization is achieved using cached semaphores. The 200-mm/sup 2/, 0.25-/spl mu/m CMOS chip operates at 100 MHz and dissipates 4 W from a 3.3-V supply.

Keywords

CMOS digital integrated circuits; cache storage; digital signal processing chips; multiprocessor interconnection networks; parallel architectures; pipeline processing; reconfigurable architectures; reduced instruction set computing; synchronisation; vector processor systems; 0.25 mum; 100 MHz; 16-b MAC/s; 3.3 V; 32 bit; 4 W; 64 bit; 64-b single-instruction; CMOS chip; DSP; DSP enhancement; MIMD multiprocessor; RISC core; cached semaphores; digital signal-processing chip; dual-ported snooping L1 cache memories; embedded RTOS; high-bandwidth data transfer; modified-MESI data coherency protocol; multiple outstanding transactions; multiple-data vector coprocessor; on-chip caches; pipelined memory controller; pipelined split transaction bus; shared memory multiprocessing; synchronization; vector reduction; Cache memory; Control systems; Coprocessors; Digital signal processing; Digital signal processing chips; Memory management; Protocols; Reduced instruction set computing; Signal processing; System-on-a-chip;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.826824

Filename

826824