Modeling of interconnect capacitance, delay, and crosstalk in VLSI

Author

Wong, Shyh-Chyi ; Lee, Gwo-Yann ; Ma, Dye-Jyun

Author_Institution

Technol. Dev. Center, Winbond Electron. Corp., Hsinchu, China

Volume

13

Issue

1

fYear

2000

fDate

2/1/2000 12:00:00 AM

Firstpage

108

Lastpage

111

Abstract

Increasing complexity in VLSI circuits makes metal interconnection a significant factor affecting circuit performance. In this paper, we first develop new closed-form capacitance formulas for two major structures in VLSI, namely: (1) parallel lines on a plane and (2) wires between two planes, by considering the electrical flux to adjacent wires and to ground separately. We then further derive closed-form solutions for the delay and crosstalk noise. The capacitance models agree well with numerical solutions of three-dimensional (3-D) Poisson equation as well as measurement data. The delay and crosstalk models agree well with SPICE simulations

Keywords

Poisson equation; SPICE; VLSI; capacitance; crosstalk; integrated circuit interconnections; integrated circuit modelling; 3D Poisson equation; SPICE simulations; VLSI circuits; circuit performance; closed-form capacitance formulas; crosstalk models; delay models; electrical flux to adjacent wires; electrical flux to ground; interconnect capacitance; metal interconnection; parallel lines on plane; wires between two planes; Capacitance measurement; Circuit optimization; Closed-form solution; Crosstalk; Delay; Integrated circuit interconnections; Poisson equations; SPICE; Very large scale integration; Wires;

fLanguage

English

Journal_Title

Semiconductor Manufacturing, IEEE Transactions on

Publisher

ieee

ISSN

0894-6507

Type

jour

DOI

10.1109/66.827350

Filename

827350