Design and implementation of OFDM timing synchronization with repeated-structured training sequence based on FPGA

Among the OFDM synchronization algorithms, the algorithm based on repeated structured training sequence is widely used because of its simple structure and high accuracy of frequency estimation. An implementation method of OFDM timing synchronization with repeated-structured training sequence is presented in this paper, which uses FPGA as a hardware platform. There are three parts in this design. The first part includes the implementation of m sequence generator module and FIFO module used to construct the training sequence. The second one is used to add the training structure generation in front of the Data symbol frame and to insert noise sequence in front of training symbol. The last part is used to find the position of the timing synchronization. We execute all of these designs by coding in Verilog-HDL and using IP Cores supplied by Xilinx ISE 13.3 software platforms. At last, all these circuits are downloaded to FPGA development board ML-605 based on XC6VLX240T-1FF1156 chip of Xilinx. Experiment results show that the timing position fall in the range of the cyclic prefix (CP) sequence, which indicates correctness and validity of the scheme designed.