Degradation Analysis of p-Type Poly-Si Thin-Film Transistors Using Device Simulation

The characteristic degradation of p-type poly-Si thin-film transistors is analyzed using a device simulation. An experiment indicates that the drain current increases under the hot-carrier stress as the stress drain bias increases. The device simulation clarifies that this degradation phenomenon can be reproduced by the electron traps at the insulator interface at least in 1 μm from the drain edge, but the electric field is high only in several hundred nanometers in the conventional trap model. This contradiction is dispelled by considering that the pseudo drain edge advances toward the channel region owing to the electron traps, allowing for a high electric field even far from the drain edge in the pseudo drain edge advance model.