A single channel, 6-bit 410-ms/s asynchronous SAR ADC based on 3bits/stage

This paper presents a single channel, low power 6-bit 410-MS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC) for wireless sensor network (WSN) applications, prototyped in a 65nm CMOS process. Through adopting the modified asynchronous binary-search successive approximation control logic and producing 3bits/stage, the proposed ADC achieves a peak spurious-free dynamic range (SFDR) of 41.95-dB, signal-to-noise and distortion ratio (SNDR) of 28.52-dB for 370 MS/s. At the sampling rate of 410 MS/s, this design still performs well with the 40.71-dB SFDR and 30.02-dB SNDR. A differential four-input dynamic comparator is designed so as to decrease the power consumption. The measurement results indicate that this SAR ADC consumes 2.03mW at a 1V power supply, corresponding to a figure of merit (FOM) of 189.17fJ/step.