• DocumentCode
    1314637
  • Title

    Snapshot sampling for ultra-high speed data acquisition

  • Author

    Wikner, J.

  • Volume
    33
  • Issue
    13
  • fYear
    1997
  • fDate
    6/19/1997 12:00:00 AM
  • Firstpage
    1137
  • Lastpage
    1139
  • Abstract
    A snapshot sampling technique is presented, which uses an optimised inverter chain for sample control and a simple sample-and-hold-circuit for highest speed and low current consumption. Simulations indicate a data acquisition time of 0.34 ns for a simple 0.8 μm digital CMOS process
  • Keywords
    CMOS integrated circuits; data acquisition; sample and hold circuits; signal sampling; 0.34 ns; 0.8 micron; current consumption; digital CMOS process; inverter chain; sample control; sample-and-hold circuit; simulation; snapshot sampling; ultra-high speed data acquisition;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19970746
  • Filename
    600984
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1314637