A 4-megacycle 18-bit checked binary counter

A multibit counter, operating within the fundamental computer cycle, is a basic tool for computation. A parallel add 1-subtract 1 system is described which is logically designed for maximum speed. Checking logic is included to detect all single errors without increasing cycle time. Current switching and emitter-follower circuits using diffused junction transistors are employed in the specific design described. The parallel counter is shown to be more efficient than an equivalent serial counter when both cost and performance are taken into account.