Nonvolatile delay flip-flop using spin-transistor architecture with spin transfer torque MTJs for power-gating systems

The power-gating (PG) ability of the authors´ previously proposed nonvolatile delay flip-flop (NV-DFF) using pseudo-spin-transistors with spin transfer torque magnetic tunnel junctions (STT-MTJs) is computationally analysed. Break-even time (BET) for nonvolatile logic circuits, which is an important index of energy performance for PG systems, is also formulated for the first time. The BET of the proposed NV-DFF can be effectively reduced by the design of the pseudo-spin-transistor parts of the cell. The NV-DFF is applicable to coarse- and fine-grained PG architectures owing to its potential BET of sub-microseconds in practical CMOS logic applications.