DocumentCode
1317026
Title
GaAs MESFET differential pass-transistor logic
Author
Pasternak, J.H. ; Salama, C.A.T.
Author_Institution
Dept. of Electr. Eng., Toronto Univ., Ont., Canada
Volume
26
Issue
19
fYear
1990
Firstpage
1597
Lastpage
1598
Abstract
A GaAs MESFET implementation of differential pass-transistor logic (DPTL) is presented. This logic technique combines the greater area efficiencies and high operation speeds of ratioless, pass-transistor circuits with the additional advantages of good noise immunity and low power dissipation. Experimental results are provided for a four-bit counter implemented in a 1 mu m, depletion (D)-mode MESFET technology to demonstrate both the functionality and noise immunity of GaAs DPTL.
Keywords
III-V semiconductors; counting circuits; field effect integrated circuits; gallium arsenide; integrated logic circuits; 1 micron; DPTL; GaAs MESFET differential pass transistor logic; GaAs transistor logic circuits; area efficiencies; circuit design; depletion mode MESFET technology; four-bit counter; noise immunity; operation speeds; power dissipation; semiconductors;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19901023
Filename
83056
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