• DocumentCode
    1317160
  • Title

    Explicit Communication and Synchronization in SARC

  • Author

    Katevenis, M.G.H. ; Papaefstathiou, Vassilis ; Kavadias, Spyros ; Pnevmatikatos, Dionisios ; Nikolopoulos, Dimitrios S. ; Silla, Federico

  • Author_Institution
    FORTH-ICS, Heraklion, Greece
  • Volume
    30
  • Issue
    5
  • fYear
    2010
  • Firstpage
    30
  • Lastpage
    41
  • Abstract
    A new network interface optimized for SARC supports synchronization and explicit communication and provides a robust mechanism for event responses. Full-system simulation of the authors´ design achieved a 10- to 40-percent speed increase over traditional cache architectures on 64 cores, a two- to four-fold decrease in on-chip network traffic, and a three- to five-fold decrease in lock and barrier latency.
  • Keywords
    network interfaces; network-on-chip; synchronisation; SARC; cache architecture; explicit communication; network interface; on-chip network traffic; Coherence; Hardware; Network interfaces; Program processors; Radiation detectors; Synchronization; SARC; configurable local memory; explicit communication; interprocessor communication; scratchpad; synchronization; user-level RDMA;
  • fLanguage
    English
  • Journal_Title
    Micro, IEEE
  • Publisher
    ieee
  • ISSN
    0272-1732
  • Type

    jour

  • DOI
    10.1109/MM.2010.77
  • Filename
    5567092
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1317160