DocumentCode
1317454
Title
A 20-nm physical gate length NMOSFET featuring 1.2 nm gate oxide, shallow implanted source and drain and BF2 pockets
Author
Deleonibus, S. ; Caillat, C. ; Guegan, G. ; Heitzmann, M. ; Nier, M.E. ; Tedesco, S. ; Dal´zotto, B. ; Martin, F. ; Mur, P. ; Papon, A.M. ; Lecarval, G. ; Biswas, S. ; Souil, D.
Author_Institution
CEA, Centre d´´Etudes Nucleaires de Grenoble, France
Volume
21
Issue
4
fYear
2000
fDate
4/1/2000 12:00:00 AM
Firstpage
173
Lastpage
175
Abstract
We have demonstrated the feasibility of 20-nm gate length NMOSFET´s using a two-step hard-mask etching technique. The gate oxide is 1.2-nm thick. We have achieved devices with real N/sup -/ arsenic implanted extensions and BF/sub 2/ pockets. The devices operate reasonably well down to 20-nm physical gate length. These devices are the shortest devices ever reported using a conventional architecture.
Keywords
MOSFET; dielectric thin films; etching; ion implantation; nanotechnology; sputter etching; 1.2 nm; 20 nm; BF/sub 2/ pockets; N/sup -/ As implanted extensions; NMOSFET; Si:As; Si:BF/sub 2/; gate length; n-MOSFET; n-channel MOSFET; shallow implanted drain; shallow implanted source; two-step hard-mask etching technique; Boron; Dielectrics; Etching; Fabrication; MOSFET circuits; Oxidation; Rapid thermal processing; Resists; Silicon; Tunneling;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/55.830972
Filename
830972
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