• DocumentCode
    1318251
  • Title

    High speed latchup resistant CMOS data output buffer for submicrometre DRAM application

  • Author

    Yoo, Hoi-Jun

  • Author_Institution
    Dept. of Electron. Eng., Kangwon Nat. Univ., Chunchon, South Korea
  • Volume
    32
  • Issue
    24
  • fYear
    1996
  • fDate
    11/21/1996 12:00:00 AM
  • Firstpage
    2229
  • Lastpage
    2230
  • Abstract
    A latchup resistant CMOS data output buffer for 0.5 μm CMOS DRAM is designed, fabricated and measured. It has a floating n-well which adjusts its voltage level to suppress the leakage current. Its leakage current is controlled to be <10 nA with the bonding pad voltage ranging from 0 to 10 V. The propagation delay is measured to be shorter by 3.8 ns than that of an NMOS data output buffer
  • Keywords
    CMOS memory circuits; DRAM chips; buffer circuits; 0 to 10 V; 0.5 micron; DRAM; bonding pad voltage; floating n-well; high speed latchup resistant CMOS data output buffer; leakage current; propagation delay;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19961516
  • Filename
    556782
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1318251