• DocumentCode
    1321022
  • Title

    On computing the minimum feedback vertex set of a directed graph by contraction operations

  • Author

    Lin, Hen-Ming ; Jou, Jing-Yang

  • Author_Institution
    Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
  • Volume
    19
  • Issue
    3
  • fYear
    2000
  • fDate
    3/1/2000 12:00:00 AM
  • Firstpage
    295
  • Lastpage
    307
  • Abstract
    Finding the minimum feedback vertex set (MFVS) in a graph is an important problem for a variety of computer-aided design (CAD) applications and graph reduction plays an important role in solving this intractable problem. This paper is largely concerned with three new and powerful reduction operations. Each of these operations defines a new class of graphs, strictly larger than the class of contractible graphs [Levy and Low (1988)] in which the MFVS can be found in polynomial-time complexity. Based on these operations, an exact algorithm run on branch and bound manner is developed. This exact algorithm uses a good heuristic to find out an initial solution and a good bounding strategy to prune the solution space. To demonstrate the efficiency of our algorithms, we have implemented our algorithms and applied them to solving the partial scan problem in ISCAS´89 benchmarks. The experimental results show that if our three new contraction operations are applied, 27 out of 31 circuits in ISCAS´89 benchmarks can be fully reduced. Otherwise, only 12 out of 31 can be fully reduced. Furthermore, for all ISCAS´89 benchmarks our exact algorithm can find the exact cutsets in less than 3 s (CPU time) on a SUN-UltraII workstation. Therefore, the new contraction operations and our algorithms are demonstrated to be very effective in the partial scan application
  • Keywords
    circuit CAD; computational complexity; directed graphs; feedback; mathematics computing; CAD applications; bounding strategy; computer-aided design; contraction operations; cutsets; directed graph; exact algorithm; graph reduction; minimum feedback vertex set; partial scan problem; polynomial-time complexity; reduction operations; Application software; Circuit testing; Design automation; Fault diagnosis; Feedback circuits; Flip-flops; Logic testing; State feedback; State-space methods; Sufficient conditions;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.833199
  • Filename
    833199