Low energy multi-stage level converter for sub-threshold logic

Robustness is the main concern in the design of level converters (LCs) for sub-threshold voltage applications. Besides this, when a sub-threshold voltage is applied to the input of the LC, the output transition time of the LC is very long and the short-circuit current through the logic gates that are driven by the LC output is large. The circuit´s total energy consumption increases. In this study, a novel single-stage LC that can operate robustly for sub-threshold signal is firstly presented. Based on the single-stage LC circuit, a multi-stage sub-threshold LC structure is proposed, which features similar operation robustness, and at the same time, greatly reduces the output transition time of the LC. As a result, the circuit´s total energy consumption (including that of the fanout logic gates) is significantly reduced. Extensive simulations were carried out to demonstrate the operation robustness of the authors proposed multi-stage sub-threshold LC. Measurements were done on a fabricated test chip to verify the operation and demonstrate the performance improvement of the design.