DocumentCode
1323381
Title
Comprehensive testing of multistage interconnection networks
Author
Mourad, Antoine ; Özden, Banu ; Malek, Miroslaw
Author_Institution
Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
Volume
40
Issue
8
fYear
1991
fDate
8/1/1991 12:00:00 AM
Firstpage
935
Lastpage
951
Abstract
The authors present efficient methods for testing packet-switched multistage interconnection networks. In addition to testing the data paths and routing capabilities, tests for detecting faults in the control circuitry including the conflict resolution capabilities are provided. Using a general model of the switch, testing sequences are constructed for the internal functions of the f ×f switch requiring only O (f 22f) tests in the case of round-robin priority and O (f 2f-1) in the case of fixed priority (f is usually a constant that is less than or equal to eight). Algorithms are then presented to test the entire network using at most twice the number of tests needed to test a switch, independently of the network size, which results in O (log N ) testing time for an N -processor network. It is shown that the method achieves higher coverage and several-orders-of-magnitude reduction in the testing time of complex multiprocessor systems compared to previous methods
Keywords
logic testing; multiprocessor interconnection networks; packet switching; O(log N) testing time; conflict resolution capabilities; data paths; multistage interconnection networks; packet-switched multistage interconnection networks; testing; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Multiprocessing systems; Multiprocessor interconnection networks; Round robin; Routing; Switches; System testing;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/12.83638
Filename
83638
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