On-chip integrated cell-level power management architecture with MPPT for PV solar system

Author

Shawky, Ahmed ; Helmy, Fatma ; Orabi, Mohamed ; Qahouq, Jaber A. ; Zhigang Dang

Author_Institution

APEARC, Aswan Univ., Aswan, Egypt

fYear

2014

fDate

16-20 March 2014

Firstpage

572

Lastpage

579

Abstract

This paper presents the design of an on-chip integrated power management architecture with Maximum Power Point Tracking (MPPT) for Photovoltaic (PV) solar system. The system is developed in order to extract higher power for PV system under partial shading and other mismatching conditions. The MPPT circuit is implemented in 0.35μm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The on-chip system utilizes a high-efficiency synchronous DC-DC boost power converter and analog Ripple Correlation Control (RCC) circuit for MPPT control. The 2400μm×5000μm developed Integrated Circuit (IC) is connected to a solar cell with 0.5V nominal output voltage and 5A output current. A peak efficiency of 92% is achieved. The design of the power stage and analog RCC MPPT algorithm circuit are presented and examined in this paper.

Keywords

CMOS integrated circuits; maximum power point trackers; solar cells; system-on-chip; CMOS technology; IC; PV solar system; analog RCC MPPT algorithm circuit; analog ripple correlation control circuit; complementary metal-oxide-semiconductor technology; high-efficiency synchronous DC-DC boost power converter; integrated circuit; maximum power point tracking; on-chip integrated cell-level power management architecture; partial shading; photovoltaic solar system; solar cell; system on-chip; Computer architecture; Integrated circuits; Logic gates; Maximum power point trackers; Photovoltaic cells; Radiation effects; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Applied Power Electronics Conference and Exposition (APEC), 2014 Twenty-Ninth Annual IEEE

Conference_Location

Fort Worth, TX

Type

conf

DOI

10.1109/APEC.2014.6803366

Filename

6803366