A 10-b, 100-MS/s CMOS A/D converter

Author

Kim, Kwang Young ; Kusayanagi, Naoya ; Abidi, Asad A.

Author_Institution

Integrated Circuits & Syst. Lab., California Univ., Los Angeles, CA, USA

Volume

32

Issue

3

fYear

1997

fDate

3/1/1997 12:00:00 AM

Firstpage

302

Lastpage

311

Abstract

A new architecture for a CMOS A/D converter overcomes many of the known problems in the parallel operation of multiple pipelined stages. The input signal is sampled in one channel, and after quantization to 4 b, the residue is distributed into many channels. A prototype implemented in 1-μm CMOS achieves 60 dB signal-to-noise plus distortion ratio (SNDR) at low conversion rates, with a resolution bandwidth of greater than 20 MHz. The SNDR drops by 3 dB at a 95 MHz conversion rate, and the bandwidth remains the same

Keywords

CMOS integrated circuits; analogue-digital conversion; integrated circuit design; integrated circuit noise; parallel architectures; pipeline processing; signal sampling; 20 MHz; 95 MHz; CMOS A/D converter architecture; conversion rate; input signal sampling; low conversion rates; multiple pipelined stages; parallel operation; quantization; residue distribution; resolution bandwidth; signal-to-noise plus distortion ratio; Bandwidth; CMOS analog integrated circuits; CMOS technology; Clocks; Dynamic range; Operational amplifiers; Pipeline processing; Prototypes; Quantization; Signal resolution;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.557627

Filename

557627