Power reduction techniques for a 1-Mb ECL-CMOS SRAM with an access time of 550 ps and an operating frequency of 900 MHz

Author

Ohhata, Kenichi ; Arakawa, Fumihiko ; Kusunoki, Takeshi ; Nambu, Hiroaki ; Kanetani, Kazuo ; Yamasaki, Kaname ; Higeta, Keiichi ; Usami, Masami ; Nishiyama, Masahiko ; Yamaguchi, Kunihiko ; Homma, Noriyuki ; Hotta, Atsuo

Author_Institution

Hitachi Device Eng. Co. Ltd., Tokyo, Japan

Volume

35

Issue

4

fYear

2000

fDate

4/1/2000 12:00:00 AM

Firstpage

564

Lastpage

571

Abstract

This paper describes power reduction circuit techniques in an ultra-high-speed emitter-coupled logic (ECL)-CMOS SRAM. Introduction of a 0.25-/spl mu/m MOS transistor allows a Y decoder and a bit-line driver to be composed of CMOS circuits, resulting in a power reduction of 34%. Moreover, a variable-impedance load has been proposed to reduce cycle time. A 1-Mb ECL-CMOS SRAM was developed by using these circuit techniques and 0.2-/spl mu/m BiCMOS technology. The fabricated SRAM has an ultrafast access time of 550 ps and a high operating frequency of 900 MHz with a power dissipation of 43 W.

Keywords

BiCMOS memory circuits; SRAM chips; emitter-coupled logic; integrated circuit design; low-power electronics; 0.2 micron; 1 Mbit; 43 W; 550 ps; 900 MHz; BiCMOS technology; ECL-CMOS SRAM; Y decoder; access time; bit-line driver; cycle time; operating frequency; power dissipation; power reduction; power reduction techniques; ultrafast access time; variable-impedance load; BiCMOS integrated circuits; CMOS logic circuits; CMOS technology; Decoding; Driver circuits; Frequency; Logic circuits; MOSFETs; Power dissipation; Random access memory;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.839916

Filename

839916