Hysteresis effect in pass-transistor-based, partially depleted SOI CMOS circuits

This paper presents a detailed study on the hysteretic delay variations of pass-transistor-based circuits with floating-body partially depleted silicon-on-insulator CMOS devices. It is shown that the pass-transistor can be conditioned into a initial state with extremely high body voltage (exceeding the power supply voltage V/sub DD/), thus resulting in highly hysteretic delay variations when the body subsequently loses charges through the switching cycles. Basic physical mechanisms underlying the hysteretic circuit behavior and its frequency dependence are examined. Different initial states of the circuit are shown to cause large delay disparity at the beginning of the switching activity, yet they converge as the circuit approaches steady state. Use of a cross coupled dual-rail circuit configuration is shown to be very effective in reducing the hysteretic delay variation and its frequency dependence.