A 1-V 6-b 50-MSamples/s current-interpolating CMOS ADC

Author

Song, Bang-Sup ; Rakers, Patrick L. ; Gillig, Steven F.

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA

Volume

35

Issue

4

fYear

2000

fDate

4/1/2000 12:00:00 AM

Firstpage

647

Lastpage

651

Abstract

CMOS analog-to-digital converters (ADC´s) require either bootstrapping techniques or low-threshold devices to function at low supply voltages. A 6-b 50-MSamples/s ADC in normal-threshold CMOS operates with a single battery cell as low as 0.9 V without bootstrapping. A current-interpolation approach is taken to configure a 1-V ADC system that does not allow more than one V/sub GS/ plus one V/sub DSsat/ between the supply rails. The prototype takes a rail-to-rail input and works with a single system clock. The chip fabricated in 0.35-/spl mu/m CMOS occupies an area of 2.4/spl times/2 mm/sup 2/ and consumes 10 mW each in analog and digital supplies.

Keywords

CMOS integrated circuits; analogue-digital conversion; integrated circuit design; interpolation; low-power electronics; 0.35 micron; 0.9 to 1 V; 10 mW; 6 bit; A/D convertor; analog-to-digital converters; current-interpolating CMOS ADC; low supply voltage; normal-threshold CMOS; rail-to-rail input; single system clock; Analog circuits; Analog-digital conversion; Batteries; CMOS analog integrated circuits; CMOS technology; Filters; Low voltage; Rails; Switches; Switching circuits;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.839926

Filename

839926