STT-RAM Cell Optimization Considering MTJ and CMOS Variations

Author

Yaojun Zhang ; Xiaobin Wang ; Hai Li ; Yiran Chen

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Pittsburgh, Pittsburgh, PA, USA

Volume

47

Issue

10

fYear

2011

Firstpage

2962

Lastpage

2965

Abstract

Spin-transfer torque random access memory (STT-RAM) becomes a promising technology for future computing systems for its fast access time, high density, nonvolatility, and small write current. However, like all the other nanotechnologies, STT-RAM suffers from process variations and environment fluctuations, which significantly affect the performance and stability of magnetic tunneling junction (MTJ) devices. In this study, we combine magnetic and circuit simulations to quantitatively analyze the impacts of MTJ and CMOS variations on the STT-RAM designs. Both bit-to-bit and cycle-by-cycle variations are considered. A robust STT-RAM design flow is also proposed.

Keywords

CMOS memory circuits; integrated circuit design; magnetic tunnelling; random-access storage; CMOS variations; MTJ devices; MTJ variation; STT-RAM cell optimization; bit-to-bit variation; circuit simulation; cycle-by-cycle variation; environment fluctuations; magnetic simulation; magnetic tunneling junction devices; nanotechnologies; process variations; robust STT-RAM design flow; spin-transfer torque random access memory; CMOS integrated circuits; MOSFETs; Magnetic tunneling; Magnetization; Switches; Torque; Magnetic random access memory (RAM); process variation; spin-transfer torque (STT);

fLanguage

English

Journal_Title

Magnetics, IEEE Transactions on

Publisher

ieee

ISSN

0018-9464

Type

jour

DOI

10.1109/TMAG.2011.2158810

Filename

6027544