A 3 Watt 39.8–44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS

Author

Nedovic, Nikola ; Kristensson, Anders ; Parikh, Samir ; Reddy, Subodh ; McLeod, Scott ; Tzartzanis, Nestoras ; Kanda, Kouichi ; Yamamoto, Takuji ; Matsubara, Satoshi ; Kibune, Masaya ; Doi, Yoshiyasu ; Ide, Satoshi ; Tsunoda, Yukito ; Yamabana, Tetsuji ;

Author_Institution

Fujitsu Labs. of America, Sunnyvale, CA, USA

Volume

45

Issue

10

fYear

2010

Firstpage

2016

Lastpage

2029

Abstract

A Dual-mode 2 ×21.5-22.3 Gb/s DQPSK or 1 × 39.8-44.6 Gb/s NRZ to 4 × 9.95-11.2 Gb/s SFI5.2-compliant two-chip SerDes for a family of 40 Gb/s optical transponders has been fabricated in 65 nm 12-metal CMOS. By demultiplexing to 16 × 2.5 Gb/s internally, all logic and testability functions could be implemented in standard-cell CMOS, resulting in total power consumption of 3 W, 75 % lower than commercial BiCMOS SFI5 40 Gb/s SerDes ICs. Chip area is 4 × 4 mm, and the ICs are flip-chip mounted into a quad flat-pack package.

Keywords

CMOS integrated circuits; flip-chip devices; optical communication equipment; phase locked loops; quadrature phase shift keying; transponders; voltage-controlled oscillators; CMOS; DQPSK; bit rate 21.5 Gbit/s to 22.3 Gbit/s; bit rate 39.8 Gbit/s to 44.6 Gbit/s; bit rate 40 Gbit/s; flip-chip; optical transponders; power 3 W; quad flat-pack package; size 65 nm; two-chip SerDes; CMOS integrated circuits; Clocks; Delay; Limiting; Optical device fabrication; Phase locked loops; Transponders; CMOS; DQPSK; SFI5.2; SerDes; Serializer; clock data recovery (CDR); common-mode logic (CML); deserializer; deskew; limiting amplifier; optical transponder; phase interpolator; phase-locked loop (PLL); voltage-controlled oscillator (VCO);

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2010.2057970

Filename

5579985