A 15-ns 32×32-b CMOS multiplier with an improved parallel structure

Author

Nagamatsu, Masato ; Tanaka, Shigeru ; Mori, Junji ; Hirano, Katsusi ; Noguchi, Tatsuo ; Hatanaka, Kazuhisa

Author_Institution

Toshiba Corp., Kawasaki, Japan

Volume

25

Issue

2

fYear

1990

fDate

4/1/1990 12:00:00 AM

Firstpage

494

Lastpage

497

Abstract

A high-speed 32×32-b parallel multiplier with an improved parallel structure using 0.8-μm CMOS triple-level-metal technology is discussed. A unit adder, a 4-2 compressor, enhances the parallelism of the multiplier array. A 25% reduction in the propagation delay time is achieved by using the compressor. The multiplier contains 27704 transistors with a 2.68-×2.71-mm² die area. The multiplication time is 15 ns at 5 V with a power dissipation of 277 mW at 10-MHz operation. The triple-level-metal interconnection technology reduces the multiplier layout area. Compared with double-level-metal technology, a 27% chip size reduction is achieved

Keywords

CMOS integrated circuits; VLSI; digital arithmetic; integrated circuit technology; integrated logic circuits; metallisation; multiplying circuits; 0.8 micron; 10 MHz; 15 ns; 2.68 mm; 2.71 mm; 277 mW; 32 bit; 5 V; CMOS; chip size reduction; compressor; layout area; multiplication time; parallel multiplier; parallel structure; power dissipation; propagation delay time; triple-level-metal technology; unit adder; Adders; CMOS technology; Digital signal processing; Laboratories; Magnetooptic recording; Parallel processing; Power dissipation; Propagation delay; Semiconductor devices; Signal processing algorithms;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.52175

Filename

52175