DocumentCode
1328775
Title
A linear-time divider array
Author
Williams, Julia ; Hamacher, V.C.
Author_Institution
Dept. of Electrical Engng., Univ. of Toronto, Toronto, Ont., Canada
Volume
6
Issue
4
fYear
1981
Firstpage
14
Lastpage
20
Abstract
Two-dimensional combinational arrays for binary division are described. A new design that generates the quotient in 0(n) time is described in detail. It is compared with earlier 0(n2) and 0(n log n) arrays. For the practical operand range of 16 through 64 bits, the 0(n) array is faster and less expensive than the 0(n log n) array. The new array also has the advantage that its logic arrangement has a more regular structure than the 0(n log n) array, and is therefore potentially more amenable to LSI implementation.
Keywords
cellular arrays; combinatorial circuits; dividing circuits; LSI implementation; binary division; design; linear-time divider array; two-dimensional combinatorial arrays; Adders; Arrays; Delays; Electrical engineering; Logic gates; Silicon; Vectors;
fLanguage
English
Journal_Title
Electrical Engineering Journal, Canadian
Publisher
ieee
ISSN
0700-9216
Type
jour
DOI
10.1109/CEEJ.1981.6593916
Filename
6593916
Link To Document