• DocumentCode
    1330681
  • Title

    SARC Coherence: Scaling Directory Cache Coherence in Performance and Power

  • Author

    Kaxiras, Stefanos ; Keramidas, Georgios

  • Author_Institution
    Inf. Technol. Dept., Uppsala Univ., Uppsala, Sweden
  • Volume
    30
  • Issue
    5
  • fYear
    2010
  • Firstpage
    54
  • Lastpage
    65
  • Abstract
    The SARC project seeks to improve power scalability of shared-memory chip multiprocessors (CMPs) by making directory coherence more efficient in both power and performance. The authors describe how they eliminate two major sources of inefficiency for directory coherence protocols: invalidation traffic on writes and directory indirection for finding the writer.
  • Keywords
    microprocessor chips; shared memory systems; SARC coherence; directory cache coherence; directory coherence protocols; power scalability; shared-memory chip multiprocessors; Coherence; Multicore processing; Protocols; Registers; Scalability; Synchronization; System-on-a-chip; SARC architecture; chip multiprocessors; directory cache coherence; power and performance scalability;
  • fLanguage
    English
  • Journal_Title
    Micro, IEEE
  • Publisher
    ieee
  • ISSN
    0272-1732
  • Type

    jour

  • DOI
    10.1109/MM.2010.82
  • Filename
    5582068
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1330681