• DocumentCode
    1331222
  • Title

    Parallel pixel processing using programmable gate arrays

  • Author

    Budgett, David M. ; Sharp, J.H. ; Chatwin, C.R. ; Young, R.C.D. ; Wang, Ruikang K. ; Scott, B.F.

  • Author_Institution
    Dept. of Mech. Eng., Glasgow Univ.
  • Volume
    32
  • Issue
    17
  • fYear
    1996
  • fDate
    8/15/1996 12:00:00 AM
  • Firstpage
    1557
  • Lastpage
    1559
  • Abstract
    A reconfigurable hardware design permits very fast feature extraction from high frame rate video images. By implementing parallel pixel processing paths in programmable gate arrays a wide range of image processing algorithms can be implemented in realtime
  • Keywords
    feature extraction; parallel architectures; programmable logic arrays; reconfigurable architectures; video signal processing; feature extraction; frame rate; image processing algorithms; parallel pixel processing; programmable gate arrays; reconfigurable hardware design; video images;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19961025
  • Filename
    533288
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1331222