Application of high pressure deuterium annealing for improving the hot carrier reliability of CMOS transistors

Author

Lee, Jinju ; Cheng, Kangguo ; Chen, Zhi ; Hess, Karl ; Lyding, Joseph W. ; Kim, Young-Kwang ; Lee, Hyui-Seung ; Kim, Young-Wug ; Suh, Kwang-Pyuk

Author_Institution

Beckman Inst. for Adv. Sci. & Technol., Illinois Univ., Urbana, IL, USA

Volume

21

Issue

5

fYear

2000

fDate

5/1/2000 12:00:00 AM

Firstpage

221

Lastpage

223

Abstract

We present the effect of high pressure deuterium annealing on hot carrier reliability improvements of CMOS transistors. High pressure annealing increases the rate of deuterium incorporation at the SiO/sub 2//Si interface. We have achieved a significant lifetime improvement (90/spl times/) from fully processed wafers (four metal layers) with nitride sidewall spacers and SiON cap layers. The improvement was determined by comparing to wafers that were annealed in a conventional hydrogen forming gas anneal. The annealing time to achieve the same level of improvement is also significantly reduced. The increased incorporation of D at high pressure was confirmed by the secondary ion mass spectrometry characterization.

Keywords

CMOS integrated circuits; MOSFET; annealing; deuterium; high-pressure effects; hot carriers; secondary ion mass spectra; semiconductor device reliability; 0.35 mum; 10 min to 3 hour; 2 to 6 atm; 3.3 V; 450 C; CMOS transistors; D incorporation rate; Si/sub 3/N/sub 4/; SiO/sub 2/-Si; SiO/sub 2//Si interface; SiON; SiON cap layers; annealing time; four metal layers; fully processed wafers; high pressure D/sub 2/ annealing; hot carrier reliability; lifetime improvement; nitride sidewall spacers; secondary ion mass spectrometry characterization; Annealing; CMOS technology; Deuterium; Electric variables; Hot carriers; Hydrogen; Mass spectroscopy; Metallization; Stress; Testing;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.841302

Filename

841302