An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing

Author

Yoshida, Yoichi ; Nose, Koichi ; Nakagawa, Yoshihiro ; Noguchi, Koichiro ; Morita, Yasuhiro ; Tago, Masamoto ; Mizuno, Masayuki ; Kuroda, Tadahiro

Author_Institution

Dept. of Electron. & Electr. Eng., Keio Univ., Yokohama, Japan

Volume

45

Issue

10

fYear

2010

Firstpage

2057

Lastpage

2065

Abstract

A small-size inductive-coupling dc voltage transceiver for highly-parallel wafer-level testing is experimentally demonstrated in 90-nm CMOS technology, which can reduce the total cost of a low-price IC by 18%. In order to carry out dc tests, the proposed transceiver outputs dc voltage to the die-under-test (DUT) without any area-consuming digital circuits. In addition, digital calibration with digital feedback channel which calibrates the output dc voltage enables the removal of calibration circuits on the DUT. All of the circuits for dc tests are implemented into the area of an inductor (100 μm ×100 μm). The proposed dc voltage transmission is successfully demonstrated with 6-bit resolution.

Keywords

CMOS digital integrated circuits; integrated circuit testing; transceivers; CMOS technology; dc voltage transmission; die-under-test; digital calibration; digital feedback channel; highly parallel wafer-level testing; inductive-coupling DC voltage transceiver; size 90 nm; Calibration; Electric potential; Needles; Testing; Transceivers; Transmitters; Wireless communication; DC test; inductive coupling; parallel test; transceiver; wafer test;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2010.2061653

Filename

5584951