Maximization of power dissipation in large CMOS circuits considering spurious transitions

With the high demand for reliability and performance, accurate estimation of maximum power dissipation in CMOS circuits is essential to determine the IR drop on supply lines and to optimize the power and ground routing. Unfortunately, the problem of determining the input patterns to induce maximum current and, hence, the maximum power, is NP complete. Even for circuits with small number of primary inputs (PIs), it is CPU time intensive to conduct exhaustive search in the input vector space. In this paper we present an automatic test generation (ATG)-based technique to efficiently generate tight lower bounds of the maximum power for large CMOS circuits under nonzero gate delays. Power dissipation due to spurious transitions has been considered by incorporating static timing analysis into the estimation process. Experiments were performed on ISCAS and MCNC benchmarks. Results show that the ATG-based technique is superior to the traditional simulation-based technique in both speed and performance. On average, for sequential circuits having over 10000 gates (ISCAS-89 benchmarks), the ATG-based approach executes 261 times faster, and generates a lower bound which is 1.8 times better compared to simulation based approaches