A VLSI architecture for arithmetic coding of multilevel images

Author

Bóo, M. ; Bruguera, J.D. ; Lang, T.

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA

Volume

45

Issue

1

fYear

1998

fDate

1/1/1998 12:00:00 AM

Firstpage

163

Lastpage

168

Abstract

We describe a VLSI architecture of an arithmetic coder for a multilevel alphabet (256 symbols) that includes the storing and updating of probabilities, the updating of the interval, and the correction of the codeword. The architecture is based on the utilization of redundant arithmetic, and the development of new schemes for storing and updating the cumulative probabilities and updating the range and left point of the current interval. The proposed implementation is compared with one that does not include these improvements, and is shown to result in a significantly lower complexity and shorter cycle

Keywords

VLSI; arithmetic codes; image coding; redundant number systems; VLSI architecture; alphabet symbol; arithmetic coding; codeword correction; interval updating; multilevel image; probability storage; probability updating; redundant arithmetic; Arithmetic; Circuits; Computer science education; Delay effects; Digital signal processing; Entropy coding; Hardware; Image coding; Libraries; Very large scale integration;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.659470

Filename

659470