Accurate analytical delay expressions for ECL and CML circuits and their applications to optimizing high-speed bipolar circuits

A linearity study of the propagation delay of bipolar circuits carried out using a SPICE program is discussed. It is found that the behavior of the propagation delay is quite linear, and therefore analytical propagation delay expressions for ECL and CML circuits are derived using a sensitivity analysis. The validity of the expressions is checked by SPICE simulations and comparison to experimental data published in the literature, and agreement is within 5%. The expressions indicate that there is an optimum value of load resistance for logic circuits in order to achieve a minimum propagation delay. For present technology, logic circuits for silicon transistors can operate at the current density corresponding to maximum f_T, and logic circuits for AlGaAs-GaAs heterojunction bipolar transistors (HBTs) should operate at a current density lower than that of maximum f_T. Therefore, it is important to increase the collector current density of maximum f_T for silicon bipolar circuits, or to decrease the base resistance R_B and the forward transit time τ_F for HBT circuits, in order to increase the circuit speed