Design and performance of a low-noise, low-power consumption CMOS charge amplifier for capacitive detectors

Author

Hu, Y. ; Solère, J.L. ; Lachartre, D. ; Tutchetta, R.

Author_Institution

LEPSI, Strasbourg, France

Volume

45

Issue

1

fYear

1998

fDate

2/1/1998 12:00:00 AM

Firstpage

119

Lastpage

123

Abstract

In this paper, a new design of low noise, low-power consumption charge amplifier is described. Theoretical results show that a total output noise voltage reduction of 0.261 mV has been obtained. This value corresponds to a 46% reduction compared to the noise performance of a conventional charge amplifier. A complete readout system including the proposed charge amplifier has been realized in a 0.8-μm semiconductor on insulator (SOI) bipolar complementary metal-oxide-semiconductor (BiCMOS) process. A measured noise performance of 450 electrons at 0 pF with a slope of 44 electrons/pF for a shaping time of 45 ns, a conversion gain of 20 mV/fC and 1-mW power consumption have been obtained.

Keywords

BiCMOS analogue integrated circuits; CMOS analogue integrated circuits; DC amplifiers; detector circuits; integrated circuit design; integrated circuit noise; nuclear electronics; silicon radiation detectors; silicon-on-insulator; 0.8 mum; 1 mW; 45 ns; BiCMOS; capacitive detectors; charge amplifier; conversion gain; low noise low-power consumption charge amplifier; low-noise low-power consumption CMOS charge amplifier; noise performance; power consumption; semiconductor on insulator bipolar complementary metal-oxide-semiconductor process; BiCMOS integrated circuits; Detectors; Electrons; Insulation; Low-noise amplifiers; Metal-insulator structures; Noise reduction; Semiconductor device noise; Semiconductor optical amplifiers; Voltage;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.659562

Filename

659562