Statistical Design Framework of Submicron Flip-Flop Circuits Considering Process Variations

In this paper, a framework for the statistical design of the flip-flops circuits is proposed to achieve a high yield, while meeting the performance, leakage power, switching power, and layout area design specifications. The proposed design solution provides the nominal design parameters, i.e., the widths and lengths of the flip-flop transistors, which provide maximum immunity to the process variations in the transistor dimensions and threshold voltage. The proposed framework shows that for a given flip-flop design specifications, a certain yield can be achieved. To further increase this yield, the proposed framework shows which design specifications should be relaxed. The transmission gate-based master-slave flip-flop is selected as a design case study in this paper, however, the proposed framework is applicable to any other flip-flop circuit in the nanometer regime.