Advanced CMOS protection device trigger mechanisms during CDM

Author

Duvvury, Charvaka ; Amerasekera, Ajith

Author_Institution

Semicond. Process & Design Center, Texas Instrum. Inc., Dallas, TX, USA

Volume

19

Issue

3

fYear

1996

fDate

7/1/1996 12:00:00 AM

Firstpage

169

Lastpage

177

Abstract

The charged device model (CDM) is now considered to be an important stress model for defining electrostatic discharge (ESD) reliability of integrated circuit (IC) chips. This paper examines the CDM performance for three different advanced protection devices in an 0.35-μm LDD complementary metal-oxide semiconductor (CMOS) technology. Through failure analysis and device simulations, the behavior of these protection devices during the CDM event is investigated. The results will enable devices to be designed for improved CDM protection levels

Keywords

CMOS integrated circuits; circuit analysis computing; digital simulation; electrostatic discharge; failure analysis; integrated circuit design; integrated circuit modelling; integrated circuit reliability; protection; 0.35 micron; CDM; IC reliability; LDD complementary metal-oxide semiconductor technology; advanced CMOS protection device; charged device model; device simulations; electrostatic discharge; failure analysis; stress model; trigger mechanisms; CMOS technology; Electrostatic discharge; Failure analysis; Integrated circuit modeling; Integrated circuit reliability; Integrated circuit technology; MOS devices; Protection; Semiconductor device modeling; Stress;

fLanguage

English

Journal_Title

Components, Packaging, and Manufacturing Technology, Part C, IEEE Transactions on

Publisher

ieee

ISSN

1083-4400

Type

jour

DOI

10.1109/3476.558865

Filename

558865