Identification of plasma-induced damage conditions in VLSI designs

Author

Simon, Paul ; Luchies, Jan Marc ; Maly, Wojciech

Author_Institution

Philips Semicond., Nijmegen, Netherlands

Volume

13

Issue

2

fYear

2000

fDate

5/1/2000 12:00:00 AM

Firstpage

136

Lastpage

144

Abstract

Typically, the plasma charging effect is investigated by using antenna test structures that do not replicate well enough conditions occurring in real VLSI integrated circuits (ICs). Consequently, understanding, modeling, and detection of plasma-charging-induced gate oxide damage in real IC´s is often inadequate. This paper discusses a new plasma-charging monitoring technique that assesses the extent of the above problem. This technique employs a multiplexed antenna monitoring (MAM) test structure with 400+ antenna configurations to determine the dependency between IC layout and the extent of gate oxide damage. The paper reports the results of application of this technique to a 0.35-μm, 75-Å gate oxide, CMOS technology. The obtained results lead to a new definition of “antenna ratio” that is supposed to capture plasma-charging conditions in real VLSI circuits

Keywords

CMOS integrated circuits; VLSI; integrated circuit layout; integrated circuit testing; plasma materials processing; process monitoring; 0.35 micron; 75 angstrom; CMOS technology; IC layout; VLSI designs; antenna ratio; gate oxide damage; multiplexed antenna monitoring; plasma charging effect; plasma-induced damage conditions; CMOS technology; Circuit testing; Degradation; Integrated circuit testing; Plasma applications; Plasma devices; Plasma materials processing; Plasma sources; Substrates; Very large scale integration;

fLanguage

English

Journal_Title

Semiconductor Manufacturing, IEEE Transactions on

Publisher

ieee

ISSN

0894-6507

Type

jour

DOI

10.1109/66.843628

Filename

843628