DC-Link Ripple Current Reduction for Paralleled Three-Phase Voltage-Source Converters With Interleaving

This paper presents a complete analysis of studying the impact of interleaving on the ripple current in the dc-side passive components of paralleled three-phase voltage-source converters (VSCs). The analysis considers the effects of different pulsewidth modulation scheme, the modulation index, the interleaving angle, and the power factor or displacement angle. In the analysis, the rms value of the total ripple current in the dc-side is used as figure of merit and calculated in the frequency domain. The results obtained show that all of the factors considered can strongly affect the rms value one way or another. Based on the analysis, the interleaving angle-optimization method is shown to minimize the rms in different cases. The effect of circulating currents on the ripple currents in the dc-side passive components is also taken into consideration to perform a more accurate analysis. All the analysis is based on an example system containing two VSCs, but the proposed analysis method in the frequency domain can be easily expandable for multiple paralleled VSCs. Experimental results are used to verify the analysis conducted.