A multilevel approach toward quadrupling the density of flash memory

Author

Kencke, David L. ; Richart, Robert ; Garg, Shyam ; Banerjee, Sanjay K.

Author_Institution

Microelectron. Res. Center, Texas Univ., Austin, TX, USA

Volume

19

Issue

3

fYear

1998

fDate

3/1/1998 12:00:00 AM

Firstpage

86

Lastpage

88

Abstract

A multilevel scheme is presented that explores the possibility of quadrupling flash EEPROM storage density. Sixteen levels (4 bits/cell) of charge are stored in existing NOR stacked gate devices. A distinction is made between logical threshold voltages (as seen by the sense amplifier) and transistor threshold voltages (as defined by the gate characteristics), and precise programming gives distinct logical threshold voltage distributions, whereas transistor threshold voltage distributions are contained in a small 2.5 V range and kept low so that logical distributions survive a ten-year equivalent data retention bake.

Keywords

EPROM; integrated memory circuits; memory architecture; multivalued logic; EEPROM; NOR stacked gate devices; equivalent data retention bake; flash memory; gate characteristics; logical threshold voltage distributions; logical threshold voltages; multilevel approach; sense amplifier; storage density; transistor threshold voltage distributions; transistor threshold voltages; Circuit testing; Distributed amplifiers; EPROM; Flash memory; Logic programming; Microelectronics; Operational amplifiers; Threshold voltage; Transistors;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.661173

Filename

661173