Investigation of interconnect capacitance characterization using charge-based capacitance measurement (CBCM) technique and three-dimensional simulation

Author

Sylvester, Dennis ; Chen, James C. ; Hu, Chenming

Author_Institution

California Univ., Berkeley, CA, USA

Volume

33

Issue

3

fYear

1998

fDate

3/1/1998 12:00:00 AM

Firstpage

449

Lastpage

453

Abstract

This paper examines the recently introduced charge-based capacitance measurement (CBCM) technique through use of a three-dimensional (3-D) interconnect simulator. This method can be used in conjunction with simulation at early process development stages to provide designers with accurate parasitic interconnect capacitances. Metal to substrate, interwire, and interlayer capacitances are each discussed and overall close agreement is found between CBCM and 3-D simulation. Full process interconnect characterization is one possible application of this new compact, high-resolution test structure

Keywords

CMOS integrated circuits; capacitance measurement; circuit analysis computing; electric charge; integrated circuit interconnections; integrated circuit measurement; 3D interconnect simulator; charge-based capacitance measurement; compact high-resolution test structure; interconnect capacitance characterization; interlayer capacitance; interwire capacitance; metal to substrate capacitance; parasitic interconnect capacitances; three-dimensional simulation; Capacitance measurement; Circuit testing; Crosstalk; Current measurement; Delay; Frequency measurement; Integrated circuit interconnections; Parasitic capacitance; Semiconductor device measurement; Substrates;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.661210

Filename

661210