On-chip measurement of the jitter transfer function of charge-pump phase-locked loops

An all-digital technique for the measurement of the jitter transfer function of charge-pump phase-locked loops (PLLs) is introduced. Input jitter may be generated using one of two methods. Both rely on delta-sigma modulation to shape the unavoidable quantization noise to high frequencies. This noise is filtered by the low-pass characteristic of the device and has little impact on the test results. For an input-output response measurement, the output jitter is compared against a threshold. As the stimulus generation and output analysis circuits are digital, do not require calibration, and demand a small area overhead, this jitter transfer function measurement scheme may be placed on the die to adaptively tune a PLL after fabrication. The technique can also implement built-in self-test (BIST) for the characterization or manufacture test of PLLs. The validity of the scheme was verified experimentally with off-the-shelf components