DocumentCode
1342347
Title
Model checking on timed-event structures
Author
Dasgupta, Pallab ; Deka, Jatindra Kumar ; Chakrabarti, P.P.
Author_Institution
Indian Inst. of Technol., Kharagpur, India
Volume
19
Issue
5
fYear
2000
fDate
5/1/2000 12:00:00 AM
Firstpage
601
Lastpage
611
Abstract
We propose a new style of model checking of timed transition systems, where instead of reasoning about the timing of states with specific properties, we reason about the timings of events with specific properties. This shift in paradigm appears to be useful for verification of edge triggered control paths, where we are more interested in the timings of changes in signal values. We propose a temporal logic, event-triggered timed computation tree logic (ETCTL), which allows the specification of event properties such as posedge(signal) and negedge(signal) along with real time computation tree logic (RTCTL) properties. We show that all ETCTL properties are interval independent, that is, their truth can never change on states between successive events. By virtue of the interval independent property, reasoning about timings of events (using ETCTL) is more efficient computationally than reasoning about general timed properties. We present a labeling algorithm, and suggest extensions to automata theoretic and symbolic approaches
Keywords
computational complexity; formal verification; logic CAD; temporal logic; timing; edge triggered control paths; event-triggered timed computation tree logic; interval independent property; labeling algorithm; model checking; real time computation tree logic properties; temporal logic; timed transition systems; timed-event structures; timing verification; Automata; Circuits; Clocks; Delay effects; Explosives; Formal verification; Hardware design languages; Labeling; Logic; Timing;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.845084
Filename
845084
Link To Document