• DocumentCode
    1342433
  • Title

    Soft-Error Rate in a Logic LSI Estimated From SET Pulse-Width Measurements

  • Author

    Makino, Takahiro ; Kobayashi, Daisuke ; Hirose, Kazuyuki ; Takahashi, Daisuke ; Ishii, Shigeru ; Kusano, Masaki ; Onoda, Shinobu ; Hirao, Toshio ; Ohshima, Takeshi

  • Author_Institution
    Dept. of Space & Astronaut. Sci., Grad. Univ. for Adv. Studies, Sagamihara, Japan
  • Volume
    56
  • Issue
    6
  • fYear
    2009
  • Firstpage
    3180
  • Lastpage
    3184
  • Abstract
    SET-induced soft-error rates (SERSETs) of logic LSIs are estimated from SET pulse-widths measured in logic cells used in logic LSIs. The estimated rates are consistent with directly measured SERSETs for logic LSIs.
  • Keywords
    MOS integrated circuits; NOR circuits; large scale integration; radiation hardening (electronics); NOR cell; NOT cell; SET pulse-width measurement; logic LSI estimation; nMOS; pMOS; single event transient; soft-error rate; Circuit testing; Clocks; Estimation theory; Extraterrestrial measurements; Filters; Frequency estimation; Large scale integration; Logic; Pulse measurements; Space vector pulse width modulation; Logic cell; SOI; single event transient; soft-error rate;
  • fLanguage
    English
  • Journal_Title
    Nuclear Science, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9499
  • Type

    jour

  • DOI
    10.1109/TNS.2009.2033795
  • Filename
    5341366
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1342433