Radiation Hardened By Design Digital I/O for High SEE and TID Immunity

Author

Clark, Lawrence T. ; Nielsen, Kyle E. ; Holbert, Keith E.

Author_Institution

Sch. of Electr., Comput., & Energy Eng., Arizona State Univ., Tempe, AZ, USA

Volume

56

Issue

6

fYear

2009

Firstpage

3408

Lastpage

3414

Abstract

Level shifting radiation hardening by design input and output (I/O) pads on a 90 nm process using triple modular redundancy for single event effect (SEE) mitigation with high total ionizing dose (TID) immunity are described. The designs use annular NMOS transistors for both thin and thick gate transistors. SEE mitigation is experimentally demonstrated by heavy ion measurements with LET_eff up to 220 MeV-cm² /mg with no failures. Measurements of the I/O standby leakage current after TID irradiation to 2 Mrad(Si) show no standby current increase.

Keywords

MOS integrated circuits; MOSFET; dosimetry; leakage currents; radiation hardening (electronics); SEE immunity; TID immunity irradiation; annular NMOS transistors; digital I/O design; heavy ion measurement; ionizing dose immunity; leakage current; radiation hardening; single event effect mitigation; thick gate transistors; thin gate transistors; Circuit testing; Current measurement; Ionizing radiation; Logic devices; MOSFETs; Radiation effects; Radiation hardening; Redundancy; Silicon on insulator technology; Voltage; Electrostatic discharge protection; input-output (I/O) circuits; radiation hardening by design (RHBD); single event effects (SEEs); single event transients (SETs); total ionizing dose (TID);

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2009.2034376

Filename

5341404